1. Technical Field
Embodiments presented herein relate generally to computing systems and processing devices, and, more particularly, to a method and apparatus for implementing a cacheable store replay policy in a processing device.
2. Description of Related Art
Electrical circuits and devices that execute instructions and process data have evolved becoming faster and more complex. With the increased performance and low power demands of modern data processor architectures (e.g., multi-core processors), committing (i.e., writing) new data (i.e., a cacheable store) to data caches has become more complex. Designing a processor capable of efficiently committing new data, while avoiding problematic conditions including contention and live-lock states, as well as power consuming events such as cache lines being repeatedly acquired by different processor cores, is particularly problematic.
In some previous solutions, acquisitions of cache lines and commits of cacheable stores were attempted after simply waiting for the cacheable store to become the oldest cacheable store in the system. In other cases, acquisitions of cache lines and commits of cacheable stores were attempted after the cacheable store was retired, and counters were implemented such that after a certain number of attempts, further attempts of acquisitions and commits of cacheable stores were performed only after the cacheable store became the oldest cacheable store in the system. These previous solutions, however, suffer from poor performance and inefficient power utilization.
Embodiments presented herein eliminate or alleviate the problems inherent in the state of the art described above.